A flash or parallel ADC is a type of analog-to-digital converter that uses a resistor ladder having multiple resistors in series and providing taps between resistors. A flash ADC converts an analog signal to a digital signal faster than other ADC architectures and provides operation across a large bandwidth, albeit at relatively low resolution. The flash ADC is widely used in high frequency applications where the higher frequency signal cannot be handled in other ways. A flash ADC operates through a cascade of high speed comparators. FIG. 1 is a simplified schematic diagram of a flash ADC 100. A reference voltage Vref 101 is provided to a number of series connected resistors 1031-103n, where n is related to the resolution bits of the flash ADC 100. The number of resistors, r, is calculated as r=2n−1 where n is the number of resolution bits. Therefore, for a 3-bit flash ADC, such as the flash ADC 100 depicted in FIG. 1, 23−1=7 resistors are required. Flash ADCs are generally limited to 8 bits of resolution. Thus, an 8-bit flash ADC would require 28−1, or 255 resistors. Each resistor 1031-103n produces a voltage drop which produces a voltage representing one significant bit of the output 117 of the flash ADC 100. Voltages associated with each resistor 103, denoted V1-Vn may be measured at corresponding nodes 1051-105n.
The analog input voltage Vin 107 is applied to a plurality of comparators 1111-111n where each comparator 111 is associated with a voltage level 105 in the reference voltage divider network 104. For each reference voltage level 105, the reference voltage is compared to the input signal voltage 109. If the input signal voltage 109 is greater than the reference voltage level 105, the corresponding comparator 111 is saturated and outputs a “1” value. If the reference voltage level 105 is greater than the input signal voltage 109, then the comparator 111 outputs a “0” value. Since each reference voltage level is lower at a given node than the reference voltage level of a preceding node (above it) in the resistor ladder, if a given comparator 111 determines that the input signal voltage 111 is higher than its corresponding reference voltage level 105 and outputs a “1”, then each comparator below that comparator in the ladder should also output a “1”. Accordingly, the set of comparators 111 outputs a series of consecutive 1's, up to the capacitor corresponding to the reference voltage level 105 closest to the input signal voltage 109; and outputs consecutive 0's for all comparators above that level. These strings of 1's and 0's are output to encoder 115, which converts them to an equivalent binary output value 117.
A comparator 111 is coupled to each tap 105, 109 of the ladder and compares the input voltage 109 to successive reference voltages 105. The output of comparators 111 is generally fed into a digital encoder 115 via latch circuits 1131-113n, which converts the inputs into a binary value output 117. Flash ADCs require a temperature compensated reference current in order to generate stable voltage drops 105 across the quantizing resistor ladder. Traditionally, this is accomplished through replica biasing. In addition, voltage drops across the resistor ladder must be trimmed to appropriate voltages to account for process variations.
Existing solutions typically trim the voltage at the emitters of the biasing transistors, either through a voltage digital to analog converter (DAC) or by directly adjusting the resistances through etching processes. Etching processes may only be performed during manufacture. However, these trimming methods introduce a non-temperature compensated offset to the voltages which degrades performance. Laser trimming of resistances within the reference circuitry may also be used. Laser trimming requires additional manufacturing steps and more robust measurement techniques during production and therefore adds significant cost to the final product. Alternative devices and methods for temperature compensated gain and mismatch trim which address one or more of these problems is desired.